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system ready, 20-bit, 2lsb inl, voltage output dac data sheet ad5790 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011-2012 analog devices, inc. all rights reserved. features single 20-bit voltage output dac, 2 lsb inl 8 nv/hz output noise spectral density 0.1 lsb long-term linearity error stability 0.018 ppm/c gain error temperature coefficient 2.5 s output voltage settling time 3.5 nv-sec midscale glitch impulse integrated precision reference buffers operating temperature range: ?40c to +125c 4 mm 5 mm lfcsp package wide power supply range of up to 16.5 v 35 mhz schmitt-triggered digital interface 1.8 v compatible digital interface applications medical instrumentation test and measurement industrial control scientific and aerospace instrumentation data acquisition systems digital gain and offset adjustment power supply control functional block diagram a1 6.8k ? 6k ? 6.8k ? r1 r fb dac reg 20 20 input shift register and control logic power-on-reset and clear logic ad5790 iov cc sdin v cc v dd v refp agnd v ss dgnd sclk sync sdo ldac clr reset r fb inv v out 20-bit dac v refn 10239-001 figure 1. table 1. related devices part no. description ad5791 20-bit, 1 lsb accurate dac ad5780 18-bit, 1 lsb inl, voltage output dac , buffered reference inputs ad5781 18-bit, 1 lsb inl, voltage output dac , unbuffered reference inputs ad5760 16-bit, 0.5 lsb inl, voltage output dac AD5541A / ad5542a 16-bit, 1 lsb accurate 5 v dac general description the ad5790 1 is a single 20-bit, unbuffered voltage-output dac that operates from a bipolar supply of up to 33 v. the ad5790 accepts a positive reference input in the range of 5 v to v dd ? 2.5 v and a negative reference input in the range of v ss + 2.5 v to 0 v. the ad5790 offers a relative accuracy specification of 2 lsb maximum range, and operation is guaranteed mono- tonic with a ?1 lsb to +3 lsb dnl specification. the part uses a versatile 3-wire serial interface that operates at clock rates of up to 35 mhz and is compatible with standard spi, qspi?, microwire?, and dsp interface standards. reference buffers are also provided on chip. the part incorpo- rates a power-on reset circuit that ensures the dac output powers up to 0 v in a known output impedance state and remains in this state until a valid write to the device takes place. the part provides a disable feature that places the output in a defined load state. the part provides an output clamp feature that places the output in a defined load state. 1 protected by u.s. patent no. 7,884,747. product highlights 1. 20-bit resolution. 2. wide power supply range of up to 16.5 v. 3. ?40c to +125c operating temperature range. 4. low 8 nv/hz noise. 5. low 0.018 ppm/c gain error temperature coefficient. companion products output amplifier buffer: ad8675 , ada4898-1 , ada4004-1 external reference: adr445 dc-to-dc design tool: adisimpower ? additional companion products on the ad5790 product page
ad5790 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? companion products ....................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings............................................................ 8 ? esd caution.................................................................................. 8 ? pin configuration and function descriptions............................. 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 18 ? theory of operation ...................................................................... 19 ? dac architecture....................................................................... 19 ? serial interface ............................................................................ 19 ? standalone operation................................................................ 20 ? hardware control pins.............................................................. 20 ? on-chip registers...................................................................... 21 ? ad5790 features ............................................................................ 24 ? power-on to 0 v......................................................................... 24 ? configuring the ad5790 .......................................................... 24 ? dac output state ...................................................................... 24 ? output amplifier configuration.............................................. 24 ? applications information .............................................................. 26 ? typical operating circuit ......................................................... 26 ? evaluation board ........................................................................ 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 2/12rev. a to rev. b deleted linearity compensation section ................................... 24 12/11rev. 0 to rev. a changes to table 1............................................................................ 1 changes to table 2............................................................................ 4 changes to figure 48...................................................................... 17 changes to dac register section ................................................ 21 changes to table 11........................................................................ 22 updated outline dimensions ....................................................... 28 11/11revision 0: initial version
data sheet ad5790 rev. b | page 3 of 28 specifications v dd = 12.5 v to 16.5 v, v ss = ?16.5 v to ?12.5 v, v refp = 10 v, v refn = ?10 v, v cc = 2.7 v to +5.5 v, iov cc = 1.71 v to 5.5 v, r l = unloaded, c l = unloaded, t min to t max , unless otherwise noted. table 2. b version 1 parameter min typ max unit test conditions/comments static performance 2 resolution 20 bits integral nonlinearity error (relative accuracy) ?2 1.2 +2 lsb v refp = +10 v, v refn = ?10 v, t a = 0c to 105c ?3 1.2 +3 lsb v refp = +10 v, v refn = ?10 v, t a =?40c to +105c ?4 1.2 +4 lsb v refx = 10 v, +10 v, and +5 v differential nonlinearity error ?1 +2 lsb v refp = +10 v, v refn = ?10 v, t a = 0c to 105c ?1 +3 lsb v refx = 10 v, +10 v, and +5 v long-term linearity error stability 3 0.1 lsb after 750 hours at t a = 135c full-scale error ?12 3.8 +12 lsb v refp = +10 v, v refn = ?10 v ?22 2.7 +22 lsb v refp = 10 v, v refn = 0 v ?40 1.8 +40 lsb v refp = 5 v, v refn = 0 v ?9 3.8 +9 lsb v refp = +10 v, v refn = ?10 v, t a = 0c to 105c ?12 2.7 +12 lsb v refp = 10 v, v refn = 0 v, t a = 0c to 105c ?22 1.8 +22 lsb v refp = 5 v, v refn = 0 v, t a = 0c to 105c full-scale error temperature coefficient 0.026 ppm/c v refp = +10 v, v refn = ?10 v zero-scale error ?19 1.3 +19 lsb v refp = +10 v, v refn = ?10 v ?40 0.7 +40 lsb v refp = 10 v, v refn = 0 v ?82 0.9 +82 lsb v refp = 5 v, v refn = 0 v ?8 1.3 +8 lsb v refp = +10 v, v refn = ?10 v, t a = 0c to 105c ?13 0.7 +13 lsb v refp = 10 v, v refn = 0 v, t a = 0c to 105c ?22 0.9 +22 lsb v refp = 5 v, v refn = 0 v, t a = 0c to 105c zero-scale error temperature coefficient 0.025 ppm/c v refp = +10 v, v refn = ?10 v gain error ?19 2.3 +19 ppm fsr v refp = +10 v, v refn = ?10 v ?35 1.9 +35 ppm fsr v refp = 10 v, v refn = 0 v ?68 0.9 +68 ppm fsr v refp = 5 v, v refn = 0 v ?9 2.3 +9 ppm fsr v refp = +10 v, v refn = ?10 v, t a = 0c to 105c ?15 2.9 +15 ppm fsr v refp = 10 v, v refn = 0 v, t a = 0c to 105c ?22 0.9 +22 ppm fsr v refp = 5 v, v refn = 0 v, t a = 0c to 105c gain error temperature coefficient 0.018 ppm/c v refp = +10 v, v refn = ?10 v r1, r fb matching 0.015 % output characteristics output voltage range v refn v refp v output voltage settling time 2.5 s 10 v step to 0.02%, using the ada4898-1 buffer in unity-gain mode 3.5 s 500 code step to 1 lsb 4 output noise spectral density 8 nv /hz at 1 khz, dac code = midscale 8 nv/hz at 10 khz, dac code = midscale output voltage noise 1.1 v p-p dac code = midscale, 0.1 hz to 10 hz bandwidth midscale glitch impulse 4 14 nv-sec v refp = +10 v, v refn = ?10 v 3.5 nv-sec v refp = 10 v, v refn = 0 v 4 nv-sec v refp = 5 v, v refn = 0 v msb segment glitch impulse 4 14 nv-sec v refp = +10 v, v refn = ?10 v, see figure 43 3.5 nv-sec v refp = 10 v, v refn = 0 v, see figure 44 4 nv-sec v refp = 5 v, v refn = 0 v, see figure 45
ad5790 data sheet rev. b | page 4 of 28 b version 1 parameter min typ max unit test conditions/comments output enabled glitch impulse 57 nv-sec on removal of output ground clamp digital feedthrough 0.27 nv-sec dc output impedance (normal mode) 3.4 k dc output impedance (output clamped to ground) 6 k reference inputs v refp input range 5 v dd ? 2.5 v v refn input range v ss + 2.5 0 v input bias current ?20 ?0.63 +20 na ?4 ?0.63 +4 t a = 0c to 105c input capacitance 1 pf v refp , v refn logic inputs input current 5 ?1 +1 a input low voltage, v il 0.3 iov cc v iov cc = 1.71 v to 5.5 v input high voltage, v ih 0.7 iov cc v iov cc = 1.71 v to 5.5 v pin capacitance 5 pf logic output (sdo) output low voltage, v ol 0.4 v iov cc = 1.71 v to 5.5 v, sinking 1 ma output high voltage, v oh iov cc ? 0.5 v iov cc = 1.71 v to 5.5 v, sourcing 1 ma high impedance leakage current 1 a high impedance output capacitance 3 pf power requirements all digital inputs at dgnd or iov cc v dd 7.5 v ss + 33 v v ss v dd ? 33 ?2.5 v v cc 2.7 5.5 v iov cc 1.71 5.5 v iov cc v cc i dd 10.3 14 ma i ss ?10 ?14 ma i cc 600 900 a ioi cc 52 140 a sdo disabled dc power supply rejection ratio 7.5 v/v ?v dd 10%, v ss = ?15 v 1.5 v/v ?v ss 10%, v dd = 15 v ac power supply rejection ratio 90 db ?v dd 200 mv, 50 hz/60 hz, v ss = ?15 v 90 db ?v ss 200 mv, 50 hz/60 hz, v dd = 15 v 1 temperature range: ?40c to +125c, ty pical conditions: t a = +25c, v dd = +15 v, v ss = ?15 v, v refp = +10 v, v refn = ?10 v. 2 performance characterized with the ad8675 arz output buffer. 3 linearity error refers to both inl error and dnl error, either parameter can be expected to drift by the amount specified afte r the length of time specified. 4 the ad5790 is configured in un ity-gain mode with a low-pa ss rc filter on the output. r = 300 , c = 143 pf (total capacitance seen by the output buffer, lead capacitance, and so forth). 5 current flowing in an individual logic pin.
data sheet ad5790 rev. b | page 5 of 28 timing characteristics v cc = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. limit 1 parameter iov cc = 1.71 v to 3.3 v iov cc = 3.3 v to 5.5 v unit test conditions/comments t 1 2 40 28 ns min sclk cycle time 92 60 ns min sclk cycle time (readback and daisy-chain modes) t 2 15 10 ns min sclk high time t 3 9 5 ns min sclk low time t 4 5 5 ns min sync to sclk falling edge setup time t 5 2 2 ns min sclk falling edge to sync rising edge hold time t 6 48 40 ns min minimum sync high time t 7 8 6 ns min sync rising edge to next sclk falling edge ignore t 8 9 7 ns min data setup time t 9 12 7 ns min data hold time t 10 13 10 ns min ldac falling edge to sync falling edge t 11 20 16 ns min sync rising edge to ldac falling edge t 12 14 11 ns min ldac pulse width low t 13 130 130 ns typ ldac falling edge to output response time t 14 130 130 ns typ sync rising edge to output response time ( ldac tied low) t 15 50 50 ns min clr pulse width low t 16 140 140 ns typ clr pulse activation time t 17 0 0 ns min sync falling edge to first sclk rising edge t 18 65 60 ns max sync rising edge to sdo tristate (c l = 50 pf) t 19 62 45 ns max sclk rising edge to sdo valid (c l = 50 pf) t 20 0 0 ns min sync rising edge to sclk rising edge ignore t 21 35 35 ns typ reset pulse width low t 22 150 150 ns typ reset pulse activation time 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iov cc ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 35 mhz for write mode and 16 mhz for readback and daisy-chain modes.
ad5790 data sheet rev. b | page 6 of 28 t 7 24 21 db23 db0 t 10 t 8 t 4 t 6 t 5 t 3 t 1 t 2 t 9 t 11 t 12 t 13 t 14 t 15 t 16 t 21 t 22 v out v out v out v out reset clr ldac sdin sync sclk 10239-002 figure 2. write mode timing diagram db23 db0 nop condition register contents clocked out t 1 t 17 t 2 t 5 t 17 t 5 t 19 t 18 t 20 t 3 t 4 t 8 t 9 t 6 t 7 24 2 2 12 4 1 db23 db0 input word specifies register to be read sdo sdin sync sclk 10239-003 figure 3. readback mode timing diagram
data sheet ad5790 rev. b | page 7 of 28 12 24 48 25 26 input word for dac n inputwordfordacn?1 input word for dac n undefined t 20 t 1 t 2 t 19 t 3 t 17 t 4 t 9 t 8 t 6 t 18 t 5 db23 db23 db0 db23 db0 db0 db23 db0 sdo sdin sync sclk 10239-004 figure 4. daisy-chain mode timing diagram
ad5790 data sheet rev. b | page 8 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 4. parameter rating v dd to agnd ?0.3 v to +34 v v ss to agnd ?34 v to +0.3 v v dd to v ss ?0.3 v to +34 v v cc to dgnd ?0.3 v to +7 v iov cc to dgnd ?0.3 v to v cc + 3 v or +7 v (whichever is less) digital inputs to dgnd ?0.3 v to iov cc + 0.3 v or +7 v (whichever is less) v out to agnd ?0.3 v to v dd + 0.3 v v refp to agnd ?0.3 v to v dd + 0.3 v v refn to agnd v ss ? 0.3 v to + 0.3 v dgnd to agnd ?0.3 v to +0.3 v operating temperature range, t a industrial ?40c to +125c storage temperature range ?65c to +150c maximum junction temperature, t j max 150c power dissipation (t j max ? t a )/ ja lfcsp package ja thermal impedance 31.0c/w lead temperature jedec industry standard soldering j-std-020 esd (human body model) 1.6 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance integrated circuit with an esd rating of <1.6 kv, and it is esd sensitive. proper precautions must be taken for handling and assembly. esd caution
data sheet ad5790 rev. b | page 9 of 28 pin configuration and fu nction descriptions inv iov cc v cc agnd v ss v ss v refn sdo dnc dnc dnc dnc sdin r fb ad5790 top view (not to scale) v out v refp reset v dd v dd clr ldac sync dgnd sclk 2 1 3 4 5 6 7 1 8 1 9 1 7 1 6 1 5 1 4 1 3 9 1 0 1 1 1 2 8 2 1 2 0 2 2 2 3 2 4 10239-005 n o t e s 1 . d n c = d o n o t c o n n e c t . d o n o t c o n n e c t t o t h i s p i n . 2 . n e g a t i v e a n a l o g s u p p l y c o n n e c t i o n ( v s s ) . a v o l t a g e i n t h e r a n g e o f ? 1 6 . 5 v t o ? 2 . 5 v c a n b e c o n n e c t e d . v s s s h o u l d b e d e c o u p l e d t o a g n d . t h e p a d d l e c a n b e l e f t e l e c t r i c a l l y u n c o n n e c t e d p r o v i d e d t h a t a s u p p l y c o n n e c t i o n i s m a d e a t t h e v s s p i n s . i t i s r e c o m m e n d e d t h a t t h e p a d d l e b e t h e r m a l l y c o n n e c t e d t o a c o p p e r p l a n e f o r e n h a n c e d t h e r m a l p e r f o r m a n c e . figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v out analog output voltage. 2 v refp positive reference voltage input. a voltage in the range of 5 v to v dd ? 2.5 v can be connected. 3, 5 v dd positive analog supply connection. a voltage in the range of 7.5 v to 16.5 v can be connected. v dd must be decoupled to agnd. 4 reset active low reset. asserting this pin returns the ad5790 to its power-on status. 6 clr active low input. asserting this pin sets the dac register to a user defined value (see table 12 ) and updates the dac output. the output value depends on the dac register coding that is being used, either binary or twos complement. 7 ldac active low load dac logic input. this is used to update the dac register and, consequently, the analog output. when tied permanently low, the outp ut is updated on the rising edge of sync . if ldac is held high during the write cycle, the input register is up dated, but the output update is he ld off until the falling edge of ldac . the ldac pin should not be left unconnected. 8 v cc digital supply. voltage range is from 2.7 v to 5.5 v. v cc should be decoupled to dgnd. 9 iov cc digital interface supply. digital threshold levels are refe renced to the voltage applied to this pin. voltage range is from 1.71 v to 5.5 v 10, 21, 22, 23 dnc do not connect. do not connect to these pins. 11 sdo serial data output. 12 sdin serial data input. this device ha s a 24-bit input shift register. data is cloc ked into the register on the falling edge of the serial clock input. 13 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 35 mhz. 14 sync level-triggered control input (active low). this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register, and da ta is then transferred in on the falling edges of the following clocks. the dac is updated on the rising edge of sync . 15 dgnd ground reference pin for digital circuitry. 16 v refn negative reference voltage input. 17, 18 v ss negative analog supply connection. a voltage in the range of ?16.5 v to ?2.5 v can be connected. v ss must be decoupled to agnd. 19 agnd ground reference pin for analog circuitry. 20 r fb feedback connection for external amplifier. see the ad5790 features section for further details. 24 inv inverting input connection for external amplifier. see the ad5790 features section for further details. epad v ss negative analog supply connection (v ss ). a voltage in the range of ?16.5 v to ?2.5 v can be connected. v ss must be decoupled to agnd. the paddle can be left electric ally unconnected provided that a supply connection is made at the v ss pins. it is recommended that the paddle be ther mally connected to a copper plane for enhanced thermal performance.
ad5790 data sheet rev. b | page 10 of 28 typical performance characteristics ?1.75 ?1.25 ?0.75 ?0.25 0.25 0.75 1.25 0 200000 400000 600000 800000 1000000 1200000 inl (lsb) dac code v refp = +10v v refn = ?10v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-006 dac code ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 200000 400000 600000 800000 1000000 1200000 inl (lsb) v refp = +5v v refn = 0v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-009 figure 6. integral nonlinearity error vs. dac code, 10 v span figure 9. integral nonlinearity error vs. dac code, 5 v span, 2 gain mode ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 200000 400000 600000 800000 1000000 1200000 inl (lsb) dac code v refp = +10v v refn = 0v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-007 0 200000 400000 600000 800000 1000000 1200000 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 dac code dnl (lsb) v refp = +10v v refn = ?10v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-010 figure 10. differential nonlinearity error vs. dac code, 10 v span figure 7. integral nonlinearity error vs. dac code, 10 v span ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 200000 400000 600000 800000 1000000 1200000 dac code dnl (lsb) v refp = +10v v refn = 0v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-011 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 200000 400000 600000 800000 1000000 1200000 dac code inl (lsb) v refp = +5v v refn = 0v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-008 figure 11. differential nonlinearity error vs. dac code, 10 v span figure 8. integral nonlinearity error vs. dac code, 5 v span
data sheet ad5790 rev. b | page 11 of 28 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 200000 400000 600000 800000 1000000 1200000 dac code dnl (lsb) v refp = +5v v refn = 0v v dd = +15v v ss = ?15v ad8675 output buffer t a = 25c 10239-012 figure 12. differential nonlinearity error vs. dac code, 5 v span ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 200000 400000 600000 800000 1000000 1200000 dnl (lsb) dac code ad8675 output buffer t a = 25c v refp = +5v v refn = 0v v dd = +15v v ss = ?15v 10239-013 figure 13. differential nonlinearity error vs. dac code, 5 v span, 2 gain mode inl error (lsb) temperature (c) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?40?200 20406080100 10v span max inl 10v span min inl +10v span max inl +10v span min inl +5v span max inl +5v span min inl v dd = +15v v ss = ?15v ad8675 output buffer 10239-014 figure 14. integral nonlinearity error vs. temperature dnl error (lsb) temperature (c) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?40 ?20 0 20 40 60 80 100 v dd = +15v v ss = ?15v ad8675 output buffer 10v span max dnl 10v span min dnl +10v span max dnl +10v span min dnl +5v span max dnl +5v span min dnl 10239-015 figure 15. differential nonlinearity error vs. temperature ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 inl error (lsb) v dd /|v ss | (v) t a = 25c v refp = +10v v refn = ?10v ad8675 output buffer inl max inl min 10239-016 figure 16. integral nonlinearity error vs. supply voltage, 10 v span ?2.2 ?1.7 ?1.2 ?0.7 ?0.2 0.3 0.8 1.3 1.8 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 inl error (lsb) v dd /|v ss | (v) t a = 25c v refp = 5v v refn = 0v ad8675 output buffer inl max inl min 10239-017 figure 17. integral nonlinearity error vs. supply voltage, 5 v span
ad5790 data sheet rev. b | page 12 of 28 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 dnl error (lsb) v dd /|v ss | (v) t a = 25c v refp = +10v v refn = ?10v ad8675 output buffer dnl max dnl min 10239-018 figure 18. differential nonlinearity error vs. supply voltage, 10 v span ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 dnl error (lsb) v dd /|v ss | (v) t a = 25c v refp = 5v v refn = 0v ad8675 output buffer dnl max dnl min 10239-019 figure 19. differential nonlinearity error vs. supply voltage, 5 v span ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 zero-scale error (lsb) v dd /|v ss | (v) t a = 25c v refp = +10v v refn = ?10v ad8675 output buffer 10239-020 figure 20. zero-scale error vs. supply voltage, 10 v span ?5 ?3 ?1 1 3 5 7 9 11 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 zero-scale error (lsb) v dd /|v ss | (v) t a = 25c v refp = 5v v refn = 0v ad8675 output buffer 10239-021 figure 21. zero-scale error vs. supply voltage, 5 v span ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ? 0.2 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 midscale error (lsb) v dd /|v ss | (v) t a = 25c v refp = +10v v refn = ?10v ad8675 output buffer 10239-022 figure 22. midscale error vs. supply voltage, 10 v span ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 midscale error (lsb) v dd /|v ss | (v) t a = 25c v refp = 5v v refn = 0v ad8675 output buffer 10239-023 figure 23. midscale error vs. supply voltage, 5 v span
data sheet ad5790 rev. b | page 13 of 28 12.5 13.0 v dd /|v ss | (v) 13.5 14.0 14.5 15.0 15.5 16.0 16.5 full-scale error (lsb) t a = 25c v refp = +10v v refn = ?10v ad8675 output buffer 10239-024 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 figure 24. full-scale error vs. supply voltage, 10 v span full-scale error (lsb) v dd /|v ss | (v) ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 t a = 25c v refp = 5v v refn = 0v ad8675 output buffer 10239-025 figure 25. full-scale error vs. supply voltage, 5 v span gain error (lsb) v dd /|v ss | (v) ?1.0 ?0.5 0 0.5 1.0 1.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 t a = 25c v refp = +10v v refn = ?10v ad8675 output buffer 10239-026 figure 26. gain error vs. supply voltage, 10 v span gain error (lsb) v dd /|v ss | (v) 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 t a = 25c v refp = 5v v refn = 0v ad8675 output buffer 10239-027 figure 27. gain error vs. supply voltage, 5 v span ?1.75 ?1.25 ?0.75 ?0.25 0.25 0.75 1.25 inl error (lsb) 5.05.56.06.57.07.58.08.59.09.510.0 t a = 25c v dd = +15v v ss = ?15v ad8675 output buffer v refp /|v refn | (v) inl max inl min 10239-028 figure 28. integral nonlinearity error vs. reference voltage ?0.25 ?0.05 0.15 0.35 0.55 0.75 0.95 1.15 dnl error (lsb) inl min inl max 5.05.56.06.57.07.58.08.59.09.510.0 t a = 25c v dd = +15v v ss = ?15v ad8675 output buffer v refp /|v refn | (v) 10239-029 figure 29. differential nonlinearity error vs. reference voltage
ad5790 data sheet rev. b | page 14 of 28 zero-scale error (lsb) v refp /|v refn | (v) 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10239-030 ?1.5 ?1.3 ?1.1 ?0.9 ?0.7 ?0.5 ?0.3 ?0.1 t a = 25c v dd = +15v v ss = ?15v ad8675 output buffer figure 30. zero-scale error vs. reference voltage midscale error (lsb) v refp /|v refn | (v) 5.05.56.06.57.07.58.08.59.09.510.0 t a = 25c v refp = +15v v refn = ?15v ad8675 output buffer 10239-031 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ? 1.0 figure 31. midscale error vs. reference voltage full-scale error (lsb) v refp /|v refn | (v) 3.5 4.0 4.5 5.0 5.5 6.0 6.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 t a = 25c v dd = +15v v ss = ?15v ad8675 output buffer 10239-032 figure 32. full-scale error vs. reference voltage gain error (lsb) v refp /|v refn | (v) 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 ?7.5 ?7.0 ?6.5 ?6.0 ?5.5 ?5.0 ?4.5 ? 4.0 t a = 25c v dd = +15v v ss = ?15v ad8675 output buffer 10239-033 figure 33. gain error vs. reference voltage full-scale error (lsb) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 ?40 ?20 0 20 40 temperature (c) 60 80 100 10v span +10v span +5v span v dd = +15v v ss = ?15v ad8675 output buffer 10239-034 figure 34. full-scale error vs. temperature midscale error (lsb) temperature (c) ?5 ?4 ?3 ?2 ?1 0 1 2 3 ?40?200 20406080100 v dd = +15v v ss = ?15v ad8675 output buffer 10v span +10v span +5v span 10239-035 figure 35. midscale error vs. temperature
data sheet ad5790 rev. b | page 15 of 28 zero-scale error (lsb) temperature (c) ?11 ?9 ?7 ?5 ?3 ?1 1 3 5 ?40 ?20 0 20 40 60 80 100 v dd = +15v v ss = ?15v ad8675 output buffer 10v span +10v span +5v span 10239-036 figure 36. zero-scale error vs. temperature gain error (lsb) ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 ?40?200 20406080100 temperature (c) v dd = +15v v ss = ?15v ad8675 output buffer 10v span +10v span +5v span 10239-037 figure 37. gain error vs. temperature 900 800 700 600 500 400 300 200 100 0 01 t a = 25c 2345 6 logic input voltage (v) ioi cc (a) iov cc = 5v, logic voltage increasing iov cc = 5v, logic voltage decreasing iov cc = 3v, logic voltage increasing iov cc = 3v, logic voltage decreasing 10239-038 figure 38. ioi cc vs. logic input voltage 0.010 0 ?0.002 0.002 ?0.004 0.004 ?0.006 0.006 ?0.008 0.008 ?0.010 ?20 ?15 ?10 ?5 0 5 10 15 20 v dd /v ss (v) i dd /i ss (ma) i dd i ss 10239-039 figure 39. power supply currents vs. power supply voltages ?10 ?8 ?6 ?4 ?2 0 2 4 6 ?1012345 v out (v) time (s) 10239-040 figure 40. rising full-scale voltage step ?1012345 time (s) ?10 ?8 ?6 ?4 ?2 0 2 4 6 v out (v) 10239-041 figure 41. falling full-scale voltage step
ad5790 data sheet rev. b | page 16 of 28 0 1 2 3 4 5 6 7 8 9 10 ?1012345 v out (mv) time (s) v refp = +10v v refn = ?10v rc low-pass filter unity gain mode ada4898-1 10239-042 figure 42. 500 code step settling time output glitch (nv-sec) code negative code change positive code change 0 5 10 15 20 25 16384 49152 81920 114688 147456 180224 212992 245760 278528 311296 344064 376832 409600 442368 475136 507904 540672 573440 606208 638976 671744 704512 737280 770048 802816 835584 868352 901120 933888 966656 999424 1032192 v refp = +10v v refn = ?10v unity gain mode ada4898-1 rc low-pass filter negative positive 10239-043 figure 43. 6 msb segment glitch energy for 10 v v ref 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 16384 65536 output glitch (nv-sec) code 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 negative positive 10239-044 v refp = 10v v refn = 0v unity gain mode ada4898-1 rc low-pass filter figure 44. 6 msb segment glitch energy for 10 v v ref 6 0 2 1 3 4 5 16384 65536 output glitch (nv-sec) code 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 negative positive 10239-045 v refp = 5v v refn = 0v unity gain mode ada4898-1 rc low-pass filter figure 45. 6 msb segment glitch energy for 5 v v ref ?25 ?15 ?5 5 15 25 35 45 55 1012 output glitch (mv) time (s) 3 v refp = +10v v refn = ?10v rc low-pass filter unity gain mode ada4898-1 10v span +10v span +5v span 10239-047 figure 46. midscale peak-to-peak glitch for 10 v 800 600 400 200 0 ?200 ?400 ?600 012345678 910 time (seconds) output voltage (nv) midscale code loaded output unbuffered ad8676 reference buffers t a = 25c v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v 10239-047 figure 47. voltage output noise, 0.1 hz to 10 hz bandwidth
data sheet ad5790 rev. b | page 17 of 28 ?20 0 20 40 60 80 100 120 140 160 180 200 0123456 output vol t age (mv) time ( s) v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v unity gain ada4898-1 10239-048 1 10 100 0.1 1 10 100 1k 10k nsd (nv/ hz) frequency (hz) v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v 10239-056 figure 48. noise spectral density vs. frequency figure 49. glitch impulse on removal of output clamp
ad5790 data sheet rev. b | page 18 of 28 terminology relative accuracy relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. a typical inl error vs. code plot is shown in figure 6 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic. a typical dnl error vs. code plot is shown in figure 10 . long-term linearity error stability linearity error long-term stability is a measure of the stability of the linearity of the dac over a long period of time. it is speci- fied in lsb for a time period of 500 hours and 1000 hours at an elevated ambient temperature. zero-scale error zero-scale error is a measure of the output error when zero-scale code (0x00000) is loaded to the dac register. ideally, the output voltage should be v refn . zero-scale error is expressed in lsbs. zero-scale error temperature coefficient zero-scale error temperature coefficient is a measure of the change in zero-scale error with a change in temperature. it is expressed in ppm fsr/c. full-scale error full-scale error is a measure of the output error when full-scale code (0x3ffff) is loaded to the dac register. ideally, the output voltage should be v refp ? 1 lsb. full-scale error is expressed in lsbs. full-scale error temperature coefficient full-scale error temperature coefficient is a measure of the change in full-scale error with a change in temperature. it is expressed in ppm fsr/c. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed in ppm of the full-scale range. gain error temperature coefficient gain error temperature coefficient is a measure of the change in gain error with a change in temperature. it is expressed in ppm fsr/c. midscale error midscale error is a measure of the output error when midscale code (0x20000) is loaded to the dac register. ideally, the output voltage should be (v refp ? v refn )/2 + v refn . midscale error is expressed in lsbs. output voltage settling time output voltage settling time is the amount of time it takes for the output voltage to settle to a specified level for a specified change in voltage. for fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 k output impedance of the ad5790 , in which case, it is the amplifier that determines the settling time. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition. see figure 49 . output enabled glitch impulse output enabled glitch impulse is the impulse injected into the analog output when the clamp to ground on the dac output is removed. it is specified as the area of the glitch in nv-sec (see figure 49 ). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of the harmonics of the dac output to the fundamental value. only the second to fifth harmonics are included. dc power supply rejection ratio dc power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the dac. it is measured for a given dc change in power supply voltage and is expressed in v/v. ac power supply rejection ratio (ac psrr) ac power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the dac. it is measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels.
data sheet ad5790 rev. b | page 19 of 28 theory of operation the ad5790 is a high accuracy, fast settling, single, 20-bit, serial input, voltage-output dac. it operates from a v dd supply voltage of 7 v to 16.5 v and a v ss supply of ?16.5 v to -2.5 v. data is written to the ad5790 in a 24-bit word format via a 3-wire serial interface. the ad5790 incorporates a power-on reset circuit that ensures the dac output powers up to 0 v with the v out pin clamped to agnd through a ~6 k internal resistor. dac architecture the architecture of the ad5790 consists of two matched dac sections. a simplified circuit diagram is shown in figure 50 . the six msbs of the 20-bit data-word are decoded to drive 63 switches, e0 to e62. each of these switches connects one of 63 matched resistors to either the buffered v refp or buffered v refn voltage. the remaining 14 bits of the data-word drive switches s0 to s13 of a 14-bit voltage mode r-2r ladder network. 2r s0 2r s1 2r s13 2r e62 2r e61 2r e0 14-bit r-2r ladder ..................... ..................... .......... ......... rr r v refp v refn v out six msbs decoded into 63 equal segments 10239-050 figure 50. dac ladder structure serial interface the ad5790 has a 3-wire serial interface ( sync , sclk, and sdin) that is compatible with spi, qspi, and microwire interface standards, as well as most dsps (see for a timing diagram). figure 2 input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk, which can operate at up to 35 mhz. the input register consists of a r/ w bit, three address bits and 20 data bits as shown in . the timing diagram for this operation is shown in . table 6 figure 2 table 6. input shift register format msb lsb db23 db22 db21 db 20 db19 to db0 r/ w register address register data table 7. decoding the input shift register r/ w register address description x 1 0 0 0 no operation (nop). used in readback operations. 0 0 0 1 write to the dac register. 0 0 1 0 write to the control register. 0 0 1 1 write to the clearcode register. 0 1 0 0 write to the software control register. 1 0 0 1 read from the dac register. 1 0 1 0 read from the control register. 1 0 1 1 read from the clearcode register. 1 x is dont care.
ad5790 data sheet rev. b | page 20 of 28 standalone operation the serial interface works with both a continuous and noncon- tinuous serial clock. a continuous sclk source can be used only if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24 th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. the input shift register is updated on the rising edge of sync . for another serial transfer to take place, sync must be brought low again. after the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. when the write cycle is complete, the output can be updated by taking ldac low while sync is high. daisy-chain operation for systems that contain several devices, the sdo pin can be used to daisy chain several devices together. daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the sdin input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n, where n is the total number of devices in the chain. when the serial transfer to all devices is complete, ad5790 sync is taken high. this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock can be a continuous or a gated clock. a continuous sclk source can be used only if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. in any one daisy-chain sequence, do not mix writes to the dac register with writes to any of the other registers. all writes to the daisy-chained parts must be either writes to the dac registers or writes to the control, clearcode, or software control register. controller data in sync sdin sclk data out serial clock control out sdo sync sclk sdo sync sclk sdo sdin sdin *additional pins omitted for clarity. ad5790* ad5790* ad5790* 10239-051 figure 51. daisy-chain block diagram readback the contents of all the on-chip registers can be read back via the sdo pin. table 7 outlines how the registers are decoded. after a register has been addres sed for a read, the next 24 clock cycles clock the data out on the sdo pin. the clocks must be applied while sync is low. when sync is returned high, the sdo pin is placed in tristate. for a read of a single register, the nop function can be used to clock out the data. alternatively, if more than one register is to be read, the data of the first register to be addressed can be clocked out at the same time the second register to be read is being addressed. the sdo pin must be enabled to complete a readback operation. the sdo pin is enabled by default. hardware control pins load dac function ( ldac ) after data has been transferred into the input register of the dac, there are two ways to update the dac register and dac output. depending on the status of both sync and ldac , one of two update modes is selected: synchronous dac update or asynchronous dac update. synchronous dac update in this mode, ldac is held low while data is being clocked into the input shift register. the dac output is updated on the rising edge of sync .
data sheet ad5790 rev. b | page 21 of 28 asynchronous dac update in this mode, ldac is held high while data is being clocked into the input shift register. the dac output is asynchronously updated by taking ldac low after sync has been taken high. the update now occurs on the falling edge of ldac . reset function ( reset ) the ad5790 can be reset to its power-on state by two means: either by asserting the reset pin or by using the software reset control function (see ). if the table 13 reset pin is not used, hardwire it to iov cc . asynchronous clear function (clr) the clr pin is an active low clear that allows the output to be cleared to a user defined value. the 20-bit clear code value is programmed to the clearcode register (see ). it is necessary to maintain table 12 clr low for a minimum amount of time to complete the operation (see ).when the figure 2 clr signal is returned high the output remains at the clear value (if ldac is high) until a new value is loaded to the dac register. the output cannot be updated with a new value while the clr pin is low. a clear operation can also be performed by setting the clr bit in the software control register (see ). table 13 on-chip registers dac register table 9 outlines how data is written to and read from the dac register. the following equation describes the ideal transfer function of the dac: ( ) refn refn refp out v dvv v + ? = 20 2 where: v refn is the negative voltage applied at the v refn input pin. v refp is the positive voltage applied at the v refp input pin. d is the 20-bit code programmed to the dac. table 8. hardware control pins truth table ldac clr reset function x 1 x x 1 0 the ad5790 is in reset mode. the device cannot be programmed. x 1 x x 1 the ad5790 is returned to its power-on state. all registers are set to their default values. 0 0 1 the dac register is loaded with the clearcod e register value and the output is set accordingly. 0 1 1 the output is set according to the dac register value. 1 0 1 the dac register is loaded with the clearcod e register value and the output is set accordingly. 1 1 the output is set according to the dac register value. 0 1 the output remains at the clearcode register value. 1 1 the output remains set according to the dac register value. 0 1 the output remains at the clearcode register value. 1 1 the dac register is loaded with the clearcode register value and the output is set accordingly. 0 1 the dac register is loaded with the clearcode register value and the output is set accordingly. 1 1 the output remains at the clearcode register value. 0 1 the output is set according to the dac register value. 1 x is dont care. table 9. dac register msb lsb db23 db22 db21 db 20 db19 to db0 r/ w register address dac register data r/ w 0 0 1 20 bits of data
ad5790 data sheet rev. b | page 22 of 28 control register the control register controls the mode of operation of the ad5790. clearcode register the clearcode register sets the value to which the dac output is set when the clr pin or clr bit in the software control register is asserted. the output value depends on the dac coding that is being used, either binary or twos complement. the default register value is 0. table 10. control register msb lsb db23 db22 db21 db20 db19 to db11 db10 db 9 db8 db7 db6 db5 db 4 db3 db2 db1 db0 r/ w register address control register data r/ w 0 1 0 reserved reserved 0000 sdodis bin/2sc dactri opgnd rbuf reserved table 11. control register functions bit name description reserved these bits are reserved and should be programmed to zero. rbuf output amplifier configuration control. 0: the internal amplifier, a1, is powered up and resistors r fb and r1 are connected in series, as shown in figure 54 . this allows an external amplifier to be connected in a gain of two configuration. see the ad5790 features section for further details. 1: (default) the internal amplifier, a1, is powered down and resistors r fb and r1 are connected in parallel, as shown in figure 53 , so that the resistance between the r fb and inv pins is 3.4 k, equal to the re sistance of the dac. this allows the r fb and inv pins to be used for input bias current compensation for an external unity-gain amplifier. see the ad5790 features section for further details. opgnd output ground clamp control. 0: the dac output clamp to ground is remo ved and the dac is placed in normal mode. 1: (default) the dac output is clamped to ground through a ~6 k resistan ce, and the dac is placed in tristate mode. resetting the part puts the dac in opgnd mode, where the output ground clamp is enable d and the dac is tristated. setting the opgnd bit to 1 in the control register overrules any write to the dactri bit. dactri dac tristate control. 0: the dac is in normal operating mode. 1: (default) dac is in tristate mode. bin/2sc dac register coding selection. 0: (default) the dac register uses twos complement coding. 1: the dac register uses offset binary coding. sdodis sdo pin enable/disable control. 0: (default) the sdo pin is enabled. 1: the sdo pin is disabled (tristate). r/ w read/write select bit. 0: ad5790 is addressed for a write operation. 1: ad5790 is addressed for a read operation. table 12. clearcode register msb lsb db23 db22 db21 db 20 db19 to db0 r/ w register address clearcode register data r/ w 0 1 1 20 bits of data
data sheet ad5790 rev. b | page 23 of 28 software control register this is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low . table 13. software control register msb lsb db23 db22 db21 db20 db19 to db3 db2 db1 db0 r/ w register address software control register data 0 1 0 0 reserved reset clr 1 ldac 2 1 the clr function has no effect when the ldac pin is low. 2 the ldac function has no effect when the clr pin is low. table 14. software control register functions bit name description ldac setting this bit to 1 updates the dac register and consequently the dac output. clr setting this bit to 1 sets the dac re gister to a user defined value (see table 12 ) and updates the dac output. the output value depends on the dac register coding that is being used, either binary or twos complement. reset setting this bit to 1 returns the ad5790 to its power-on state.
ad5790 data sheet rev. b | page 24 of 28 ad5790 features power-on to 0 v the ad5790 contains a power-on reset circuit that, as well as resetting all registers to their default values, controls the output voltage during power-up. upon power-on, the dac is placed in tristate (its reference inputs are disconnected), and its output is clamped to agnd through a ~6 k resistor. the dac remains in this state until programmed otherwise via the control register. this is a useful feature in applications where it is important to know the state of the dac output while it is in the process of powering up. configuring the ad5790 after power-on, the ad5790 must be configured to put it into normal operating mode before programming the output. to do this, the control register must be programmed. the dac is removed from tristate by clearing the dactri bit, and the output clamp is removed by clearing the opgnd bit. at this point, the output goes to v refn , unless an alternative value is first programmed to the dac register. dac output state the dac output can be placed in one of three states, controlled by the dactri and opgnd bits of the control register, as shown in table 15 . table 15. output state truth table dactri opgnd output state 0 0 normal operating mode 0 1 output is clamped via ~6 k to agnd 1 0 output is in tristate 1 1 output is clamped via ~6 k to agnd output amplifier configuration there are a number of different ways that an output amplifier can be connected to the ad5790 , depending on the voltage references applied and the desired output voltage span. unity-gain configuration figure 52 shows an output amplifier configured for unity gain. in this configuration, the output spans from v refn to v refp . a1 6.8k ? 6.8k ? r1 r fb v refp r fb inv v out v out 20-bit dac v refn ad5790 ad8675 ada4898-1 ada4004-1 10239-052 figure 52. output amplifier in unity-gain configuration a second unity-gain configuration for the output amplifier is one that removes an offset from the input bias currents of the amplifier. it does this by inserting a resistance in the feedback path of the amplifier that is equal to the output resistance of the dac. the dac output resistance is 3.4 k. by connecting r1 and r fb in parallel, a resistance equal to the dac resistance is available on chip. because the resistors are all on one piece of silicon, they are temperature coefficient matched. to enable this mode of operation the rbuf bit of the control register must be set to logic 1. figure 53 shows how the output amplifier is connected to the ad5790 . in this configuration, the output amplifier is in unity gain and the output spans from v refn to v refp . this unity-gain configuration allows a capacitor to be placed in the amplifier feedback path to improve dynamic performance. v refp r fb inv v out v out 10pf 20-bit dac v refn = 0v ad5790 ad8675 ada4898-1 ada4004-1 r fb 6.8k ? r1 6.8k ? 10239-053 figure 53. output amplifier in unity gain with amplifier input bias current compensation
data sheet ad5790 rev. b | page 25 of 28 gain of two configuration (2 gain mode) figure 54 shows an output amplifier configured for a gain of two. the gain is set by the internal matched 6.8 k resistors, which are exactly twice the dac resistance, having the effect of removing an offset from the input bias current of the external amplifier. in this configuration, the output spans from 2 v refn ? v refp to v refp . this configuration is used to generate a bipolar output span from a single ended reference input with v refn = 0 v. for this mode of operation, the rbuf bit of the control register must be cleared to logic 0. a1 6.8k ? 6.8k ? r1 r fb v refp r fb inv v out v out 10pf 20-bit dac v refn ad5790 ad8675 ada4898-1 ada4004-1 10239-054 figure 54. output amplifier in gain of two configuration
ad5790 data sheet rev. b | page 26 of 28 applications information typical operating circuit 10239-055 figure 55. typical operating circuit
data sheet ad5790 rev. b | page 27 of 28 figure 55 shows a typical operating circuit for the ad5790 using an ad8675 as an output buffer. because the output impedance of the ad5790 is 3.4 k, an output buffer is required for driving low resistive, high capacitive loads. evaluation board an evaluation board is available for the ad5790 to aid designers in evaluating the high performance of the part with minimum effort. the ad5790 evaluation kit includes a populated and tested ad5790 printed circuit board (pcb). the evaluation board interfaces to the usb port of a pc. soft- ware is available with the evaluation board to allow the user to easily program the ad5790 . the software runs on any pc that has microsoft? windows? xp (sp2), or vista (32-bit or 64-bit), or windows 7 installed. the ad5790 user guide, ug-342, is available, which gives full details on the operation of the evaluation board.
ad5790 data sheet rev. b | page 28 of 28 outline dimensions 122409-b bottom view top view 0.30 0.25 0.20 1.00 0.90 0.80 1 7 8 12 13 19 20 24 5.00 bsc 4.00 bsc pin 1 indicator (chamfer 0.225) 3.75 3.65 3.50 2.75 2.65 2.50 exposed pad seating plane pin 1 indicator 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.50 bsc 0.50 0.40 0.30 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 56. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 5 mm body, very thin quad (cp-24-5) dimensions shown in millimeters ordering guide model 1 temperature range inl package description package option ad5790bcpz ?40c to +125c 4 lsb 24-lead lfcsp_vq cp-24-5 ad5790bcpz-rl7 ?40c to +125c 4 lsb 24-lead lfcsp_vq cp-24-5 eval-ad5790sdz evaluation board 1 z = rohs compliant part. ?2011-2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10239-0-2/12(b)

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